1. Field of the Invention
The present invention is directed generally to transistors and more specifically to a method for manufacturing lateral bipolar transistors.
2. Description of the Related Art
Currently, integrated bipolar transistors arc primarily constructed in the form of vertical transistors having npn layers or pnp layers arranged above one another. Given this vertical structure, two layers of this layer sequence are not directly accessible, i.e. from the surface, but must be laterally extended and subsequently conducted up to the surface. A further, highly doped layer is generally necessary for the lowest doped layer in order to keep the conduction to the surface adequately low-impedance.
The disadvantage of this arrangement is that vertical transistors have a noteworthy depth expanse, typically one-two .mu.m, and lateral dimensions that multiply exceed the region claimed by the actual transistor. Correspondingly, there are a number of parasitic capacitances and resistances that, in addition to causing a possible loss in the switching speed, noticeably increase the power consumption above all else.
Also, the complexity of the manufacturing process and the area requirements of these components are extremely high compared to MOS components, thereby leading to low yields and high manufacturing outlays. The simultaneous manufacture of complementary structures (npn and pnp transistors), for example, for analog applications, is only possible with a considerable outlay. A lateral arrangement of a bipolar transistor is usually manufactured such that zones for emitter and collector are produced by locally limited re-doping in a region that is doped for the conductivity type of the base and is also relatively vertically extensive.